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Operating Modes
9.3.4.1 Watchdog Pulse (Mode 9)
Bit Settings
Mode Characteristics
TC3
1
TC2
0
TC1
0
TC0
1
Mode
9
Name
Pulse
Function
Watchdog
TIO
Output
Clock
Internal
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to the
period of one timer clock. After the counter reaches the value in the TCPR, if the TCSR[TRM]
bit is set, the counter is loaded with the TLR value on the next timer clock and the count resumes.
Therefore TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the
counter continues to increment on each subsequent timer clock. This process repeats until the
timer is disabled (that is, TCSR[TE] is cleared). If the counter overflows, a pulse is output on the
TIO signal with a pulse width equal to the timer clock period. If the INV bit is set, the pulse
polarity is high (logical 1). If INV is cleared, the pulse polarity is low (logical 0). The counter
reloads when the TLR is written with a new value while the TCSR[TE] bit is set. In Mode 9,
internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after
the hardware RESET signal is asserted. This convention ensures that a valid RESET signal is
generated when the TIO signal resets the DSP56311.
first event
Mode 9 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
(Software does not reset watchdog timer; watchdog times out)
TRM = 1 is not useful for watchdog function
TLR
N
Counter (TCR)
0
N
N+1
M
M+1
0
1
TCPR
M
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
TIO pin (INV = 0)
float
TIO pin (INV = 1)
low
high
pulse width
= timer
clock period
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Figure 9-18. Watchdog Pulse Mode
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
9-19
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